The critical dimension (CD) of transistors is continuous scaled down as integration level of semiconductor chips increases. As the CD of transistors is scaled down below 130 nm, the mainstream process in metal inter connection field to gradually use copper interconnection instead of aluminum interconnection because of the high resistance characteristic of aluminum. The widely-used method to manufacture copper interconnections is using damascene process as inlaying technology, and the trench-first dual damascene process is one of methods to form copper wire interconnections and copper VIA-holes in one-step. FIG. 1a-1f diagrams structural flow of the trench-first dual damascene process. Depositing a low-k dielectric layer 12 on the silicon substrate layer 11 as is shown in FIG. 1a; Coating a first photoresist 13 on the low-k dielectric layer as is shown in FIG. 1b; Removing the first photoresist 13 to form a metal trench structure 14 in the low-k dielectric layer 12 using lithography and etch technology as is shown in FIG. 1c; Coating a second photoresist 15 on the upper surface of the low-k dielectric layer 12, and coating the second photoresist on the side-wall and the bottom of the metal trench structure 14 as is shown in FIG. 1d; Then removing the second dielectric 15 to form a VIA hole 16 through metal trench structure 14 and reaching on the upper surface of the substrate layer 11 using lithography and etch technology as is shown in FIG. 1e; Filling metal material in the metal trench structure 14 and the VIA hole 16 to form metal interconnection line disposed in the first metal trench 17 and VIA-hole metal 18 using metal deposition and CMP technology.
When the CD of transistors is scaled down below 32 nm, a single exposure process is not enough to meet the resolution requirement in manufacturing dense line array pattern, so dense line array pattern of which the CD is below 32 nm is formed wildly using double patterning technique. FIG. 2a-2e is flow diagrams of the double patterning technique. As is shown in FIG. 2a, sequentially depositing substrate film 22, hard mask 23 and first photoresist 24 on the silicon substrate 21; As is shown in FIG. 2b, removing the first photoresist 24 using exposure, development and etching technology, and forming a first line pattern 25 and a metal trench structure 26, which the CD ratio of the line pattern 25 and the metal trench structure 26 is 1:3; As is shown in 2c, coating a second photoresist 27 on the upper surface and the side face of the first line pattern 25, the side-wall and the bottom of the metal trench structure 26 and the upper surface of the substrate film 22; As is shown in FIG. 2d, forming a second line pattern 28 in the second photoresist 27 using exposure and development technology, meanwhile removing the rest second photoresist 27, and the CD ratio of the second line pattern 28 and the metal trench structure 26 is also 1:3, which the second line pattern 28 is in the middle of the metal trench structure 26; As is shown in FIG. 2e, removing the first line pattern 25 and the second line pattern 28 on the substrate film 22 using etching technology, and forming a target line 29 and a metal trench structure 210, the CD ratio of the target line 29 and the metal trench structure 210 is 1:1, which means the combination of the target line 29 and the metal trench structure 210 can form dense line array pattern. The double patterning technique needs two times of lithography and etch processes, which means the cost is much more than the traditional single exposure technology. Hence, it is desired to develop new techniques to reduce the cost of double patterning technique. The US patent US20100190104 disclosed a method that coating polymer curing material containing alkoxy group after developing the first photoresist pattern, to cure the first photoresist pattern in the first photoresist. The double patterning process with this method can be simplified to be litho-litho-etch, which omits the first etching step in the former process, so as to effectively reduce the cost of the double patterning technique. And this method is also known as double exposure technique.